Historically, a variety of power systems architectures have been used, principal among them Centralized Power Architecture (CPA), Distributed Power Architecture (DPA), and Intermediate Bus Architecture (IBA). With each generation of processor, memory, DSP, and ASIC, the trend to lower voltages at higher currents continues to challenge the infrastructure needed to support contemporary "loads" with the necessary mix of power and current.
CPA, one of the oldest power systems architectures, generates all system voltages at a central location and distributes them to load locations via distribution buses. This can be effective if the voltages are high and the currents low or if the distances between the power supply and the loads are small. However, for low voltages and widely distributed loads, the problem of distribution losses becomes unmanageable. Since the 1980s, the bricks of DPA have delivered the classic functions of the dc-dc converter (isolation, voltage transformation, and regulation) to the Point of Load, but at a price in terms of premium space and cost. To deal with the multiplicity of low voltages, IBA turned to niPOLs (non-isolated buck step down regulators), reducing the POL function to regulation from a low voltage bus. But niPOLs have an inherent conflict, rooted in fundamental physics, between efficient power distribution and efficient power conversion duty cycle.
A new power conversion architecture, called Factorized Power Architecture™ or FPA, has been developed, and new families of enabling power components, called V·I Chips™ or VICs, have been introduced. With FPA, isolated Voltage Transformation Modules™ (VTM) are deployed at the point-of-load, and regulation is provided by Pre-Regulator Modules™ (PRM) that can be located, or "factorized," away from the point-of-load. In combination, the PRM and VTM perform all of the classic functions of a dc-dc converter. The PRM generates a controlled bus voltage, called the "factorized bus voltage," that is delivered to the input of a VTM. The VTM transforms the factorized bus voltage to deliver an isolated lower (or higher) voltage to the point-of-load. Load regulation is performed using feedback to the upstream PRM; the PRM adjusts the factorized bus voltage to maintain the load voltage in regulation. (A recently introduced product incorporating V·I Chip technology is the VICBrick™, shown above, a quarter-brick sized, high-performance dc-dc converter that conforms to industry standard footprints and pin-outs, while delivering high performance in power density, efficiency, transient response, and cost.)
Families of V·I Chip VTMs and PRMs, optimized for different nominal input and output voltages, and packaged commensurate with their power capabilities, provide the power systems designer with a stable of conversion components that can be used to economically solve a virtually limitless variety of power conversion problems. Specifically, Factorized Power overcomes the distribution losses, low duty cycles, slow response, and dependency on bulk capacitance that inherently limits the applicability of the Intermediate Bus Architecture. V·I Chips offer small, low-profile power solutions with low noise, high efficiency, fast transient response, and low cost. (Chart shows efficiency vs load for a VICBrick model with standard output of 1.5 V at 80 A.)